RTL design and FPGA implementation of a high speed multiplier

A multiplier unit is a significant module of a processing unit. After reviewing the available literature, it is observed that the speed of the existing conventional multiplier is limited by the processing delays in the adders used for the partial product addition. This thesis has addressed high speed multiplication process by using the splitting technique, and Carry Save Adder (CSA) which reduces the propagation delay of the addition process. The designed module is described and tested using EDA tools such as ModelSim, Quartus Prime Lite Edition, and Altera DE2 Board. All possible numbers are being checked by the brute-force checking module in ModelSim. According to our analysis report, an 8-bit multiplier required 114 logic elements (LE) and 32 registers. Total thermal power dissipation of the multiplier is 141.39 mW, core dynamic thermal power dissipation is 0.00 mW, core static thermal power dissipation is 98.50 mW, and I/O thermal power dissipation is 42.89 mW. From the time analysis it is found that maximum operating speed is 1.066 GHz.

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